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december 2009 doc id 16819 rev 2 1/24 1 L5962 multiple linear/switching vo ltage regulator for car-radio features step-down synchronous switching voltage regulator ? internal high-side/ low-side ndmos ?1.2 < v out < 8 v selectable through external resistors ? 1.2/2.5 a load current selected through dedicated pin ? 185 khz free-run frequency ? sync function (220 < f sw < 400 khz) linear regulators ? 3.3/5 v @ 150 ma standby regulator selected through dedicated pin (vstbysel) ? 5/8.5 v @ 350 ma switched linear regulator enabled and selected through i 2 c bus (vlr1) ? 3.3/10 v @ 1 a switched linear regulator enabled and selected through i 2 c bus (vlr2) 2 high side drivers (0.5 v max drop @ 0.5 a) enabled through i 2 c bus and equipped with protection circuit against: ? short to ground and battery ? loss of ground and battery ? unsupplied short to battery reset function with configurable delay (rst, rstdly) i 2 c bus enable pin to drive switching regulator and i 2 c bus logic under/over voltage battery detector (vbatvw) ? under voltage threshold adjustable through dedicated pin (lvwin) load dump protection independent thermal protection on all regulators description L5962 is a very versatile device exploiting bcd technology characteristic s to provide a complete set of regulated voltages covering all the needs of a car-radio set. in standby condition the device guarantees extremely low quiescent current (90 a max - 40 c < t < 85 c) and minimum operating voltage (4.5 v using an external schottky diode for the back-up function). powerso36 (slug-up) table 1. device summary order code package packing L5962 powerso36 tray L5962tr powerso36 tape and reel www.st.com
contents L5962 2/24 doc id 16819 rev 2 contents 1 block and application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1.1 linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1.2 switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 high side drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 battery detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6i 2 c bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2 start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3 byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 software specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
L5962 list of tables doc id 16819 rev 2 3/24 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. chip address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. ib1 data byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8. vlr2 output level selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 9. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
list of figures L5962 4/24 doc id 16819 rev 2 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. low voltage warning high level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 5. data validity on the i 2 c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6. timing diagram on the i 2 c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7. acknowledge on the i 2 c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 8. powerso36 (slug-up) mechanical data and pack age dimensions . . . . . . . . . . . . . . . . . . . 22
L5962 block and application diagram doc id 16819 rev 2 5/24 1 block and application diagram figure 1. block diagram sda switching regulator linear regulator #2 linear regulator #1 standby regulator hsd hsd reset & delay uv / ov detect bandgap reference por & startup logic clock synch logic oscillator scl rstdly rst vbatvw synch en hsd2 hsd1 vlr2 vlr1 vstby vbatp ph cbs clim vfb vinsw ground agnd pgnd external storage vcmp vbat tab sost vstbysel subs lvwin vinlr2 i2cbus logic ac00428
block and application diagram L5962 6/24 doc id 16819 rev 2 figure 2. application diagram tab 1 pgnd 2 cbs 3 phase 4 nc 5 nc 6 subgnd 7 vinsw 8 hsd1 9 vbat 10 hsd2 11 vbatp 12 rstdly 13 vstby 14 vstbys 15 agnd 16 nc 17 nc 18 36 nc 35 nc 34 clim 33 vfb 32 vcmp 31 sost 30 sync 29 scl 28 en 27 reset 26 vlr2 25 vinlr 24 sda 23 vlr1 22 vbatw 21 lvwin 20 nc 19 nc L5962 1 0.1 0.1f 22h 200u/10v 470 3.3nf 22k 22k/(vdcout-1) 75k 1.8nf 2.7nf en vbatw sync reset 2.2 vstby scl sda 30/35v 4.7 0.1 0.1 0.1 470/25v r1 r2 10k vstby 0.1 1 0.1 1 47k vbat 10k vbat vdcout hsd1 hsd2 vstby vlr2 vlr1 1500pf 22 47k +5v +5v 0.1 s1 s2 s3 1000u/50v
L5962 pin description doc id 16819 rev 2 7/24 2 pin description figure 3. pin connection (top view) n.c. n.c. agnd vstbysel n.c. ph n.c. cbs pgnd n.c. clim vfb sost vcmp vbatw lvwin n.c. n.c. 18 16 17 15 6 5 4 3 2 21 22 31 32 33 35 34 36 20 1 19 tab n.c. ac00429 hsd1 subgnd vinsw sync en scl 9 8 7 28 29 30 vbat rst 10 27 vstby hsd2 vbatp vlr2 vlr1 vinlr2 14 12 11 23 25 26 rstdly sda 13 24 table 2. pin description pin # pad name function description 1 tab this pin must be connected to gnd 2 pgnd switching regulator ground it is the power ground reference 3 cbs bootstrap for switching regulator bootstrap capacitor input for the switching regulator 4 ph switching stage output phase output. it is the switching output of the switching regulator. it also provides phase reference for bootstrap drive. 5 n.c. not connected - 6 n.c. not connected - 7 subgnd substrate ground substrate ground 8 vinsw switching regulator supply voltage battery voltage for the switching regulator 9 hsd1 high side driver 1 output of the 1 st high side driver 10 vbat vlr1/hsd1/hsd2 supply voltage voltage input for linear regulator #1 high side driver and battery warnings 11 hsd2 high side driver 2 output of the 2 nd high side driver 12 vbatp standby regulator supply voltage protected battery input for bias, bandgap, oscillator, and vstby regulator 13 rstdly reset delay function input 14 vstby standby regulator output output of the standby regulator
pin description L5962 8/24 doc id 16819 rev 2 15 vstbysel standby regulator selector selection input for standby regulator output (3.3 v or 5 v) 16 agnd analog ground analog voltage reference 17 n.c. not connected - 18 n.c. not connected - 19 n.c. not connected - 20 n.c. not connected - 21 lvwin battery detector adjustme nt input low-voltage warning input 22 vbatw battery detector output (open-drain) battery voltage warning output 23 vlr1 switched linear regul ator 1 output of the 1 st linear regulator 24 sda i 2 c bus data i 2 c data line 25 vinlr2 vlr2 supply voltage battery supply for the 2 nd linear regulator 26 vlr2 switched linear regul ator 2 output of the 2 nd linear regulator 27 rst reset output 28 en enable active mode enable input. active high 29 scl i 2 c bus clock i 2 c clock source supplied by the master device 30 sync switching regulator sync function synchronization input 31 sost switching regulato r soft-start soft start external capacitor 32 vcmp switching regulator compensation feedback compensation input. 33 vfb switching regulator feedback regulated output voltage sense 34 clim switching regulator current limit selector choose between two current limits 35 n.c. not connected - 36 n.c. not connected - table 2. pin description (continued) pin # pad name function description
L5962 electrical specification doc id 16819 rev 2 9/24 3 electrical specification 3.1 absolute maximum ratings 3.2 thermal data 3.3 electrical characteristics vbat= vinsw = vinlr2 = 14.4 v, t amb = 25 c unless otherwise specified. ( table 3. absolute maximum ratings pin name/symbol parameter value unit vs max operating supply voltage (vbat, vbatp, vinsw, vinlr2) -0.3 to 27 v transient supply voltage (vbat, vbatp, vinsw, vinlr2) -0.3 to 50 v vpin max input pin voltage (en, rstdly, vstbysel, synch, scl, sda, vcmp, vfb, clim, sost) -0.3 to 6 v agnd, pgnd, subgnd, tab ground pin voltage -0.3 to +0.3 v t op operating temperature range -40 to 85 c t stg storage temperature range -55 to 150 c table 4. thermal data symbol parameter value unit r th j-case thermal resistance junction-to-case (max) 2 c/w table 5. electrical characteristics symbol parameter test conditions min. typ. max. unit input supplies v min vbatp operating voltage - 4.1 - - v i q total quiescent current en = 0; i vstby =100 a @ t = -40 c @ 25 c < t < 85 c --90 75 a v ov overvoltage shut-down vbat rising 27 29 31 v hys ov hysteresis on v ov --400-mv v uv vbat undervoltage threshold vbat falling; vbatvw transition to 0 v 77.58 v
electrical specification L5962 10/24 doc id 16819 rev 2 hys uv hysteresis on v uv --1-v vstby (3.3 v) vout vstby3 output voltage 0 < i load < 150 ma 3.2 3.3 3.4 v lnr vstby3 line regulation 4.1 50s c = 1 f ceramic --5% psrr vstby3 power supply rejection ratio i load = 50 ma 120 hz < f < 10 khz vbatp ac = 1 vpp 70 - - db n vstby3 output noise a-weighted filter 20 hz < f < 20 khz i load = 5 ma --200v ts vstby3 thermal shut-down temperature temperature rising 150 - 190 c hys ts-vstby3 hysteresis on thermal shut- down temperature -5-15c esr vstby3 external filtering capac itor esr c > 0.5 f - - 0.2 vstby (5 v) vout vstby5 output voltage 0 < i load < 150 ma 4.80 5 5.15 v lnr vstby5 line regulation 6 50s c = 1 f ceramic --5% psrr vstby5 power supply rejection ratio i load = 50 ma 120 hz < f < 10 khz vbatp ac =1 vpp 70 - - db n vstby5 output noise a-weighted filter 20 hz < f < 20 khz i load = 5 ma --200v ts vstby5 thermal shut-down temperature temperature rising 150 - 190 c hys ts- vstby5 hysteresis on thermal shut- down temperature -5-15c esr vstby5 external filtering capac itor esr c > 0.5 f - - 0.2 table 5. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit
L5962 electrical specification doc id 16819 rev 2 11/24 vlr1 (5 v) vout vlr1-5 output voltage 0 < i load < 350 ma 4.85 5 5.15 v lnr vlr1-5 line regulation 6 50s c = 1 f ceramic --3% psrr vlr1-5 power supply rejection ratio i load = 170 ma 120 hz < f < 10 khz vbat ac =1 vpp 60 - - db n vlr1-5 output noise a-weighted filter 20 hz < f < 20 khz i load = 5 ma --350v ts vlr1-5 thermal shut-down temperature temperature rising 150 - 190 c hys ts-vlr1-5 hysteresis on thermal shut- down temperature -5-15c esr vlr1-5 external filtering capac itor esr c > 0.5 f - - 0.2 vlr1 (8.5 v) vout vlr1-8 output voltage 0 < i load < 350 ma 8.3 8.5 8.7 v lnr vlr1-8 line regulation 9.6 50s c = 1 f ceramic --3% psrr vlr1-8 power supply rejection ratio i load = 170 ma 120 hz < f < 10 khz vbat ac =1 vpp 60 - - db n vlr1-8 output noise a-weighted filter 20 hz < f < 20 khz i load = 5 ma --350v ts vlr1-8 thermal shut-down temperature temperature rising 150 - 190 c hys ts-vlr1-8 hysteresis on thermal shut- down temperature -5-15c esr vlr1-8 external filtering capac itor esr c > 0.5 f - - 0.2 table 5. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit
electrical specification L5962 12/24 doc id 16819 rev 2 vlr2 (3.3 v) vout vlr2-3 output voltage 0 < i load < 1 a 3.2 3.3 3.4 v lnr vlr2-3 line regulation 4.5 < vinlr2 < 18 v i load = 1 a -20 - +20 mv ldr vlr2-3 load regulation 0 < i load < 1 a -70 - - mv vdo vlr2-3 drop out voltage i load = 1 a - - 1.2 v ishort vlr2-3 short circuit current limit 1.5 - 2.5 a os/us vlr2-3 overshoot / undershoot i load 0 ? 1a, t > 50s c = 1 f ceramic --3% psrr vlr2-3 power supply rejection ratio i load = 500 ma 120 hz < f < 10 khz vinlr2 ac =1 vpp 60 - - db n vlr2-3 output noise a-weighted filter 20hz0.5f - - 0.2 vlr2 (10 v) vout vlr2-10 output voltage 0 50 s c = 1 f ceramic --3% psrr vlr2-10 power supply rejection ratio i load = 500 ma 120 hz 0.5 f - - 0.2 table 5. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit
L5962 electrical specification doc id 16819 rev 2 13/24 hsd1 vdrop hsd1 output saturation i load = 0.5 a - - 500 mv ileak hsd1 leakage current hsd off output shorted to gnd --10a ishort hsd1 short circuit current limit - 0.75 - 1.5 a ts hsd1 thermal shut-down temperature temperature rising 150 - 190 c hys ts-hsd1 hysteresis on thermal shut- down temperature -5-15c hsd2 vdrop hsd2 output saturation i load = 0.5 a - - 500 mv ileak hsd2 leakage current hsd off output shorted to gnd --10a ishort hsd2 short circuit current limit - 0.75 - 1.5 a ts hsd2 thermal shut-down temperature temperature rising 150 - 190 c hys ts-hsd2 hysteresis on thermal shut- down temperature -5-15c switching regulator vout sw output voltage selectable through external resistor divider 1.2 - 8 v i loadmaxsw load current limitation v outsw decreasing of 100 mv (1) clim = 0 v clim = 5 v 1.2 2.5 - 3 6 a f sw free-run switching frequency - 150 180 210 khz v fb fb voltage - 970 - 1030 mv vdrop sw dropout voltage vout sw = 8 v iload sw = 2.5 a (1) --1.2v f sync switching frequency selectable through sync pin - 220 - 400 khz efficiency free run frequency (1) v outsw = 8 v; i load = 2.5 a 85 - - % sr ss soft-start pin slew rate c sost = 10 nf (1) --10v/ms ts sw thermal shut-down temperature temperature rising 150 - 190 c hys sw hysteresis on thermal shut- down temperature -5-15c table 5. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit
electrical specification L5962 14/24 doc id 16819 rev 2 reset function thr rst reset threshold on vstby vstby = 3.3 v 93 - 98 % hys rst hysteresis on rst - 30 - 150 mv vsat rst rst pin saturation voltage i rst = 0.5 ma - - 0.4 v dly rst rst delay time c = 100 pf on rstdly pin 25 - 75 s tfall rst rst fall time r = 47 k c = 50 pf --1s tglitch rst glitch filter time for rst - 5 - 20 s thr rstdly rstdly pin threshold rst falling 3 - 3.7 v i rstdly rstdly output current rstdly = off 7 - 13 a controls thr en en minimum level recognized as high -2--v en maximum level recognized as low --0.8v hys en hysteresis on en - 150 - - mv leak en en pin leakage current - -1 - 1 a thr clim clim pin threshold -0.8-- v --2 leak clim clim pin leakage current - -1 - 1 a thr lv w i n lvwin threshold - 1.225 - 1.275 v hyst lv w i n lvwin hysteresis - 100 - 200 mv i 2 c bus thr scl clock minimum level recognized as high -2.2--v clock maximum level recognized as low ---0.8v thr sda data minimum level recognized as high -2.2--v data maximum level recognized as low ---0.8v f scl clock frequency - - - 400 khz 1. by bench characterization table 5. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit
L5962 device description doc id 16819 rev 2 15/24 4 device description the ic includes one standby regulator, always active to guarantee the standby functions; two switched linear regulators, managed by the i 2 c bus and a step-down switching voltage regulator with select able current limit. 4.1 regulators the vstby regulator is always active when the ic is supplied. the other regulators can be enabled or disabled. their outputs are automatically disabled whenever the vbat voltage exceeds the over-voltage shutdown threshold. upon return from over-voltage shutdown, the outputs recover without intervention from the system. 4.1.1 linear regulators vstby (3.3 v / 5.0 v standby) vstby is a linearly regulated 3.3/5 v output. this output is enabled on battery connect. it is supplied from the protected battery input (vbatp). in order to select the 3.3 v output, the vstbysel pin mu st be connect ed to ground. in order to select the 5. 0 v output, the vstbysel pin must be connected to 5 v. when the dropout voltage of the regulator cannot be maintained, the output shall track the vbatp input voltage less the saturation voltage of the regulator pass element. this regulator has a short circuit protection consisting of current limit, and thermal shutdown. if the local die temperature exceeds the thermal shutdown detection threshold, the output is disabled. the thermal shutdown circuitry has hysteresis such that the output is enabled only after the die temperature falls below the thermal shutdown disable threshold. thermal shutdown on this output doesn't directly disable any other circuitry. rst provides an indication that vstby is in regulation. it is an open drain output used to indicate that vstby is in regulation (below the low-voltage threshold). rst remains low until vstby achieves regulation and the rstdly input has charged to its threshold. for instance, rst remains low during battery connect and disconnect and under low-voltage battery lockout. the transition from standby mode to active mode (and vice versa) does not cause the rst output to be triggered. rstdly provides a means to delay the releasing of rst once vstby has achieved regulation. it is used to delay the release of rst when vstby achieves regulation. this input has a current source to charge an external capacitor and an internal pull-down to discharge the external capacitor. the voltag e on this capacitor is used to control the operation of the rst output. the rstdly pull-down is activated when a loss of regulation is detected. the input remains low until vstby once again achieves regulation. when the rstdly is released the current source charges the external capacitor. when the voltage exceeds the pin's threshold, rst pin is also released, disabling its pull-down.
device description L5962 16/24 doc id 16819 rev 2 vlr1 (5.0 v /8.5 v) and vlr2 (3.3 v, 5.0 v, 5.5 v, 6.0 v, 7.0 v, 7.5 v, 8.0 v, 10.0 v) the output of these two regulators can be selected through the i 2 c bus. when the dropout voltage of the regulator cannot be maintained, the output tracks the vbat input voltage less the saturation voltage of the regulator pass element. this regulator has a short circuit protection cons isting of current limit and thermal shutdown. if the local die temperature exceeds the thermal shutdown detection threshold, the output is disabled. the thermal shutdown circuitry has hyst eresis such that the output is enabled only after the die temperature falls below the thermal shutdown disable threshold. thermal shutdown on this output doesn't directly disable any other circuitry. vlr2 has its own power supply (vinlr2) because of its high current capability. 4.1.2 switching regulator the ic contains an independent, step-down, synchronous switching regulator, which is used to produce an output voltage that is adjustable in the system by means of an external resistor divider. the switching regulator functionality is guaranteed in the 1.2-8.0 v output voltage range. the switching frequency is externally synchronizable. the switcher has its own supply input pin (vinsw) and is enabled by the en input. the regulator contains soft-start control to protect external devices from excessive in-rush currents. this control is independent of th e presence of a synchronizing signal on the synch input. the switching cycle is synchroniz ed to the internal oscillator unless a signal is present on the sync input. the signal present on the synch input overrides the internal oscillator to control the switching of the regulator if its frequency gets inside the allowed range (220- 400 khz). the ic detects a small number of edges (e.g. 2-5) prior to recognize a valid input signal and synchronizing internal operation to the external signal. it is designed to operate in continuous conduction mode (ccm), where the inductor current remains continuous throughout the entire load range of the output. it can also work in dcm mode. this regulator has short circuit protection co nsisting of cycle-by-cyc le duty-cycle limitation. upon return from over-voltage shutdown this regulator employs the soft-start. an external bootstrap capacitor must be connected between the output (ph, phase output pin) and the cbs pin. the switching regulator output slew rate can be controlled with an external capacitor on the sost (soft start) pin. this protects the device against excessive dv/dt transients, lowering the stress of the internal components. a maximum slews rate of 10 v/ms is suggested. two separate current limits for the switching regulator can be chosen in order to guarantee a proper protection for the device at the desired load current rating. the clim pin should be tied to ground for the low limit (max 3 a) or to 5.0 v for the high limit (max 6 a). the vfb pin is the voltage feedback from the regulated output for the switching regulator; the vcmp one is the compensation feedback for the switching regulator.
L5962 device description doc id 16819 rev 2 17/24 4.2 high side drivers the device embeds fully-protected high-side drivers for use outside of the car-radio module. hsd1, hsd2 these high side driver outputs have short circui t protections consisting of current limit and independent thermal shutdown. if the local die temperature exceeds the thermal shutdown detection threshold, the output is disabled. the thermal shutdown circuitry has hysteresis such that the output is enabled only after the die temperature falls below the thermal shutdown disable threshold. thermal shutdown on any one output doesn't directly disable any other circuitry. hsd1 and hsd2 are protected from shorts to ground and shorts to battery (0-18 v) during a loss of car-radio module battery.
operating mode L5962 18/24 doc id 16819 rev 2 5 operating mode when a power source is connected to the ic, the internal circuitry begins to establish internal bias, the bandgap reference voltage, and other related functions. the standby (vstby) regulator and battery detection are functional. the standby mode is activated when the enable (en) input is asserted low. when the enable (en) input is set high (en =1: active mode.), the ic exits the standby mode and enters the active mode. during active mode, i2c interface is activa ted and all functions are operational. the ic remains in active mode until either the standby regulator falls out of regulation (where the ic enters the low-voltage reset state) or until the enable (en) input is brought back to 0 v (where the ic enters the standby state). 5.1 battery detection the operating voltage for vlr1, high side drivers and battery warnings is provided by vbat pin. this input is also used as reference to detect an over-voltage or an under-voltage condition. when such condition is detected, the vbatvw output is pulled down. the overvoltage detection circuit has hysteresis for noise rejection. two external resistors (rext1, rext2), whose values are lower than 100 kohm, are connected to the lwin (low warn ing input) pin to give the possi bility to trim the threshold at which the low voltage warning comparator trig gers. when lvwin voltage is below the input voltage threshold (1.25 v typ), the vbatw (battery voltage warning) output is pulled down and a low-voltage warning is indicated. when no external resistor network is connected to lvwin, the detector sets the threshold to a nominal 7.5 v. no external interaction is requ ired to reset the output state, because it is automatically reset when the fault condition is removed. figure 4 shows an high level block diagram of th e low-voltage warning circuit. vbat is divided by two internal resistors (rint1, rint2) and two external programming resistors (rext1, rext2). when vbat decreases so that lvwin voltage gets lower than the internal reference (vbg), vbatw is pulled down to ground. figure 4. low voltage warning high level block diagram vbat rint1 =13.89 m ohm rint2 = 2.83 m ohm rext1 rext2 vbatw vbg lvwin comparator
L5962 i 2 c bus interface doc id 16819 rev 2 19/24 6 i 2 c bus interface data transmission from microprocessor to the L5962 and viceversa takes place through the 2 wires i 2 c bus interface, consisting of the two lines sda and scl (pull-up resistors to positive supply voltage must be connected). 6.1 data validity as shown by figure 5 , the data on the sda line must be stable during the high period of the clock. the high and low state of the data line can only change when the clock signal on the scl line is low. 6.2 start and stop conditions as shown by figure 6 a start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high transition of the sda line while scl is high. 6.3 byte format every byte transferred to the sda line must contain 8 bits. each byte must be followed by an acknowledge bit. the msb is transferred first. 6.4 acknowledge the transmitter* puts a resistive high level on the sda line during the acknowledge clock pulse (see figure 6 ). the receiver** the acknowledges has to pull-down (low) the sda line during the acknowledge clock pulse, so that the sdaline is stable low during this clock pulse. * transmitter ? master (p) when it writes an address to the L5962 ? slave (L5962) when the p reads a data byte from L5962 ** receiver ? slave (L5962) when the p writes an address to the L5962 ? master (p) when it reads a data byte from L5962 figure 5. data validity on the i 2 c bus sda scl data line stable, data valid change data allowed d99au1031
i 2 c bus interface L5962 20/24 doc id 16819 rev 2 figure 6. timing diagram on the i 2 c bus figure 7. acknowledge on the i 2 c bus scl sda start i 2 cbus stop d99au1032 scl 1 msb 23789 sda start acknowledgment from receiver d99au1033
L5962 software specifications doc id 16819 rev 2 21/24 7 software specifications ic functions can be driven sending one data byte ib1 bits d6-d4 are used to select vlr2 output voltage according to the following table table 6. chip address d7 (msb) d0 (lsb) 0001000r/w10 hex table 7. ib1 data byte bit position bit name function description d7 vlr2en vlr2 enable d6 vlr2sel2 vlr2 selection d5 vlr2sel1 d4 vlr2sel0 d3 vlr1en vlr1 enable d2 vlr1sel vlr1 selection d1 hsd2en hsd2 enable d0 hsd1en hsd1 enable table 8. vlr2 output level selection vlr2sel2 vlr2sel1 vlr2sel0 vlr2 output voltage 0 0 0 3.3v 0 0 1 5.0v 0 1 0 5.5v 0 1 1 6.0v 1 0 0 7.0v 1 0 1 7.5v 1 1 0 8.0v 1 1 1 10.0v
package information L5962 22/24 doc id 16819 rev 2 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 8. powerso36 (slug-up) mechanical data and package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 3.270 - 3.410 0.1287 - 0.1343 a2 3.100 - 3.180 0.1220 - 0.1252 a4 0.800 - 1.000 0.0315 - 0.0394 a5 - 0.200 - - 0.0079 - a1 0.030 - -0.040 0.0012 - -0.0016 b 0.220 - 0.380 0.0087 - 0.0150 c 0.230 - 0.320 0.0091 - 0.0126 d 15.800 - 16.000 0.6220 - 0.6299 d1 9.400 - 9.800 0.3701 - 0.3858 d2 - 1.000 - - 0.0394 - e 13.900 - 14.500 0.5472 - 0.5709 e1 10.900 - 11.100 0.4291 - 0.4370 e2 - - 2.900 - - 0.1142 e3 5.800 - 6.200 0.2283 - 0.2441 e4 2.900 - 3.200 0.1142 - 0.1260 e - 0.650 - - 0.0256 - e3 - 11.050 - - 0.4350 - g 0 - 0.075 0 - 0.0031 h 15.500 - 15.900 0.6102 - 0.6260 h - - 1.100 - - 0.0433 l 0.800 - 1.100 0.0315 - 0.0433 n - - 10? - - 10? s - -8?- -8? (1) ?d and e1? do not include mold flash or protusions. mold flash or protusions shall not exceed 0.15mm (0.006?). (2) no intrusion allowed inwards the leads. powerso36 (slug up) 7183931 g
L5962 revision history doc id 16819 rev 2 23/24 9 revision history table 9. document revision history date revision changes 24-nov-2009 1 initial release. 10-dec-2009 2 updated figure 8: powerso36 (slug-up) mechanical data and package dimensions on page 22 .
L5962 24/24 doc id 16819 rev 2 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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